the Andrew Bailey

Registers of the ARM CPU Architecture

Advanced RISC Machine CPUs, or ARM, have taken over the world in the past 10 years. Although this architecture has been around since the 1980s, it's only with the proliferation of cellphones and their monthly replacement cycles that they have outnumbered everything else. Up until then, they were mostly found in low power applications, like microcontrollers. I find it strange that the same CPU architecture can power some people's most loved and most hated CPUs.

As the name suggests, it is a RISC based design like Power. A more illustrative term would be "load-store". Like x86, there are different numbers of registers, depending on the architecture version. Up to ARM v7, registers were 32-bit. R0 to R15 are general purpose registers. R15 is the program counter. R8 to R14 are banked, or renamed, depending on what mode the CPU is in. For example, in FIQ mode, R8 to R14 are R8_fiq to R14_fiq. R13 and R14 are the stack pointer and link register, and due to their special status, they have many more banked names. There is a Current Program Status Register CPSR, and a Saved Program Status Register SPSR, which is only accessible in privileged CPU modes.

From ARM v8, AArch64 was introduced. It requires floating point capability, and removes the silly register banking business, for the most part. There are 64-bit general purpose registers, X0-X30. X30 is also the Link Register, and there is a separate Stack Pointer register. The bottom 32 bits of X0-X30 are W0-W30. These are accompanied by a Media Register File that contains 32 registers 128-bit wide. The whole 128 bits are V0-V31, the bottom 64 bits are D0-D31, and the bottom 32 bits are S0-S31.

I guess the bottom line is that programming for a power efficient architecture is not simple.

Posted under Programming.

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