the Andrew Bailey

Registers of the Alpha CPU Architecture

Alpha CPUs are pretty obscure these days, and they also seem to be obsolete. This architecture is a load-store or RISC design, and it was one of the first 64-bit ones out there. It was largely optimized by hand, just right when CPU designs were starting to be automated, leading to competitive performance. There was a version of Windows NT released for it, and its floating point performance was superior to x86.

There are 32 general purpose integer registers, R0 to R31, along with 32 double precision floating point registers, F0 to F31. R31 and F31 are hard wired to 0 and 0.0; writes to them are ignored. There is a Program Counter register that has the lowest 2 bits always set to 0. There are to lock registers, LR0 and LR1, along with an FP Control Register. All registers are 64-bit.

During the latter 90s, DEC (the Alpha CPU designers) worked with AMD. In fact, AMD hired one of their designers, Dirk Meyer, who led the design on the original Athlon (K7) CPU. Unfortunately, Compaq and HP would drop system and designs for this soon after Itanium hit, sometime around 2004 or so. The intellectual property was later bought by Intel, probably to guarantee that it would never be used again.

Posted under Programming.

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